Analog-to-digital converters (ADCs) convert an analog input that is a sample of an analog signal into a corresponding digital representation. This invention relates to multistage converters and in particular to multistage analog-to-digital converters employing dither to reduce non-linearity.
Analog-to-digital converters (ADCs) convert an analog input that is a sample of an analog signal into a corresponding digital representation. Multiple stage ADCs include a plurality of stages, each of which converts a portion of the analog input, and each of which contributes to the digital representation. Multistage converters receive the analog input in a first stage for processing. The first stage determines one or more bits. A residue representing the portion of the analog input not converted by that or previous stages is generated and passed to a subsequent stage for processing to determine one or more additional bits. This process continues through each of the stages of the converter. When each stage completes processing the analog input or residue, each stage is ready to receive a new analog input or residue to process. One type of multiple stage converter is known as a pipelined converter. Due to the time required to fill the pipeline, pipelining causes an initial latency in computing the digital representation corresponding to an analog input sample. However, pipelining increases the rate at which digital representations corresponding to sequential analog input samples are generated by the converter due to parallel processing of the samples.
Each stage of a multistage ADC may produce more bits than the output of that stage represents in a digital representation of a sample of the analog input to the first stage of the converter, providing some redundancy of information for error correction. Error correction may be employed to ease the circuit design requirements for the internal circuitry of the converter. An error corrector circuit receives the bit or bits produced by each stage of the multistage converter, skewed in time, and generates a corresponding digital output, digital representation, or digital word that is representative of the sample of the analog input. The error corrector circuit output can also be the digital output from the multistage converter.
Multistage converters are disclosed in various publications, including xe2x80x9cA 10-b 20-Msample/s Analog-to-Digital Converterxe2x80x9d, by Lewis, et al, IEEE Journal of Solid State Circuits, Mar. 1992, Vol. 27, pp. 351-358, Analog Integrated Circuits Design, by D. A. Johns and K. Martin, as well as U.S. patent application Ser. No. 09/025,956, the disclosures of which are hereby incorporated by reference.
One known technique to reduce non-linearity in an analog-to-digital converters is to add random noise to the input signal. Adding random noise to the input signal reduces the signal-to-noise ratio of the converter. To reduce non-linearity without reducing the signal-to-noise ratio, random noise energy may be added to the signal in a portion of the available frequency spectrum that is not of interest. However, for this technique to be useful in a particular application, there must be a portion of the available frequency spectrum that is not of interest where the noise can be added. In applications requiring the full range of available bandwidth for a signal, this technique can not be used. Furthermore, this technique reduces the dynamic range of a converter in which it is employed.
Various non-idealities which may be present in an ADC result in non-linearities in the ADC transfer function and a corresponding reduction in performance. To meet the accuracy requirements as defined by the bits of ADC resolution, the non-linearities must not exceed one least significant bit (LSB) in magnitude. Although the non-linearities in a pipelined ADC may be less than one LSB, they may have a repetitive or periodic nature, which results in the generation of spurious tones in the frequency spectra of the digital representation of the analog input. An important measure of an ADC""s performance is spurious free dynamic range (SFDR), which is defined in the frequency domain as the amplitude difference between a spectrally pure input signal and the highest non-input signal component present in the frequency spectra of the ADC""s digital output representation of the analog input signal. Some of the non-idealities that affect the SFDR performance of pipelined converters are, finite opamp gain, capacitor matching, and reference voltage variations.
What is needed is a technique to improve the ADC SFDR. Given the presence these non-idealities, one way to alter the SFDR performance of a pipelined converter is to change the placement of comparator thresholds. In a pipelined converter, randomly varying the comparator thresholds within a correctable range, a form of dithering, improves the ADC SFDR by spreading the energy that previously had been present in spurious tones over a wider frequency range but with a lower amplitude. Such a technique would retain the desirable aspects of introducing dither without consuming a portion of the available frequency spectrum or reducing the dynamic range of the converter, thereby leaving the entire available frequency spectrum for signal bandwidth.
In accordance with the invention, a multistage converter and method for converting a sampled analog signal to a corresponding digital representation. Each stage of the converter receives an analog input signal and produces a partial digital output. A voltage range, having a lower limit and an upper limit, is defined over which samples of the input analog signal can vary. A first stage receives the sampled analog signal as the analog input signal. Each stage except a last stage provides a residue output, which is the analog input signal to a subsequent stage. The residue is the analog input signal to the stage less the partial digital output from the stage, possibly with a gain change.
A lower comparator threshold is established between the lower limit and upper limit of the voltage range. An upper comparator threshold is established within the voltage range, the upper comparator threshold being between the lower comparator threshold and the upper limit. The internal error correction circuitry allows each of these two thresholds to vary over a predetermined range without causing errors greater than one LSB in the transfer function of the ADC. Thresholds are intentionally placed at the extreme ends of two correctable comparator ranges defining a correctable error range. A third threshold is established in the center of the correctable error range where the two correctable comparator ranges meet, at the bottom end of the upper comparator correctable range and the top end of the lower comparator correctable range. This third threshold defines the middle comparator threshold.
The analog input to the stage is quantized based on the lower comparator threshold, middle comparator threshold, and upper comparator threshold to generate a digital word which is representative of the region within the conversion voltage range in which the analog input resides. When the quantized analog input signal falls between the upper comparator threshold and middle comparator threshold, the digital word representative of the region in which the analog input resides may at the end of each quantization cycle be randomly changed (dithered), without causing errors greater than one LSB in the transfer function of the ADC, to reflect that the analog input had been between the upper end of the conversion range and the upper comparator threshold. Similarly, when the quantized analog input signal falls between the middle comparator threshold and lower comparator threshold, the digital word representative of the region in which the analog input resides may at the end of each quantization cycle be randomly changed (dithered), without causing errors greater than one LSB in the transfer function of the ADC, to reflect that the analog input was between the lower comparator threshold and the lower end of the voltage range. The effect of this dither is to randomly create threshold errors that are correctable by the ADC architecture.
The partial digital outputs from each stage are provided to an error corrector circuit that removes redundancy and effects of the dither when generating the digital representation corresponding to the sampled analog input.